Read e-book online CPU Design: Answers to Frequently Asked Questions PDF

By Chandra Thimmannagari

ISBN-10: 0387237992

ISBN-13: 9780387237992

Offers details in a undemanding, easy-access approach in order that the publication can act as both a short reference for more matured engineers or as an introductory consultant for brand new engineers and school graduates.

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CPU Design: Answers to Frequently Asked Questions 38 Table 8: Pseudo LRU Algorithms 3. Use the following algorithm to update the 3-bit LRU vector in the case of a Cache Hit 4. Use the following algorithm to update the 3-bit LRU vector in the case of a Snoop Invalidate 5. Use the following algorithm to replace an entry and update the 3-bit LRU vector in the case of a Cache Miss 3 3-bit UVL Pseudo LRU algorithm as applied to a 4-Way Set Associative Cache Mem- ory Architecture 39 Table 8: Pseudo LRU Algorithms 1.

E the address to index any byte within the Main Memory). Since the size of L1Cache (L1$) is 256B and the Line size is 1B, L1Data will hold 256 lines from Main Memory and L1Tag will hold 256 Tag address where each Tag address corresponds to a Line in L1Data. e 1Byte in this case) on every access from L1$ and since L1$ is 128x2 entries (L1$ being 2-Way Set Associative), we need 7-bits to index L1Data and L1Tag arrays. Since Main Memory is 16KB, we will have a maximum of 2 Pages (16KB/8KB=2) sitting in Main Memory at any given time.

Use the following algorithm to update the 3-bit UVL vector in the case of a Cache Hit 4. Use the following algorithm to update the 3-bit UVL vector in the case of a Snoop Invalidate CPU Design: Answers to Frequently Asked Questions 42 Table 8: Pseudo LRU Algorithms 5. Use the following algorithm to replace an entry and update the 3-bit UVL vector and round_robin bit in the case of a Cache Miss 5 8-bit Pseudo LRU algorithm as applied to a 4-Way Set Associative Cache Memory Architecture 43 Table 8: Pseudo LRU Algorithms 1.

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CPU Design: Answers to Frequently Asked Questions by Chandra Thimmannagari


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